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PHD108NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 -- 5 June 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Simple gate drive required due to low gate charge Suitable for logic level gate drive sources
1.3 Applications
DC-to-DC convertors Switched-mode power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 5 V; see Figure 1; see Figure 3 Tmb = 25 C; see Figure 2 Min Typ Max 25 75 187 Unit V A W drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation Symbol Parameter
Avalance ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 12 V; Tj = 25 C; see Figure 12; see Figure 13 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10; see Figure 11 5.6 nC VGS = 10 V; Tj(init) = 25 C; ID = 43 A; Vsup 25 V; unclamped; tp = 0.25 ms; RGS = 50 180 mJ
Static characteristics RDSon drain-source on-state resistance 5.3 6 m
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain
2 1 3
Simplified outline [1]
mb
Graphic symbol
D
G
mbb076
S
SOT428 (SC-63; DPAK)
[1] It is not possible to make a connection to pin 2.
3. Ordering information
Table 3. Ordering information Package Name PHD108NQ03LT SC-63; DPAK Description plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) Version SOT428 Type number
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)S Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 5 V; Tmb = 25 C; see Figure 1; see Figure 3 VGS = 5 V; Tmb = 100 C; see Figure 1 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 175 C Tj 25 C; Tj 175 C; RGS = 20 k Min -20 -55 -55 Max 25 25 20 75 75 240 187 175 175 75 240 180 Unit V V V A A A W C C A A mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalance ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 43 A; Vsup 25 V; drain-source avalanche unclamped; tp = 0.25 ms; RGS = 50 energy
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
2 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
120 Ider (%) 80
03ar58
120 Pder (%) 80
03aa16
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
03ar59
103 ID (A) 102 Limit RDSon = VDS / ID tp = 10 s 100 s
DC 10
1 ms 10 ms
1 1 10 VDS (V) 102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
3 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ Max 0.8 Unit K/W thermal resistance from see Figure 4 junction to mounting base thermal resistance from minimum footprint; mounted on a junction to ambient printed-circuit board; vertical in still air mounted on a printed-circuit board; vertical in still air; SOT404 minimum footprint
Rth(j-a)
-
75 50
-
K/W K/W
1 = 0.5
03ar60
Zth(j-mb) (K/W)
0.2 10-1 0.1 0.05
P = tp T
0.02 single pulse
tp
t T
10
-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 250 A; VGS = 0 V; Tj = -55 C ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8; see Figure 9 ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 8; see Figure 9 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 8; see Figure 9 IDSS IGSS drain leakage current gate leakage current VDS = 25 V; VGS = 0 V; Tj = 25 C VDS = 25 V; VGS = 0 V; Tj = 175 C VGS = 10 V; VDS = 0 V; Tj = 25 C VGS = -10 V; VDS = 0 V; Tj = 25 C
PHD108NQ03LT_4
Min 25 22 1 0.5 -
Typ 1.5 0.02 0.02
Max 2 2.2 1 500 100 100
Unit V V V V V A A nA nA
4 of 12
Static characteristics
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
Table 6. Symbol RDSon
Characteristics ...continued Parameter drain-source on-state resistance Conditions VGS = 5 V; ID = 25 A; Tj = 25 C; see Figure 10; see Figure 11 VGS = 5 V; ID = 25 A; Tj = 175 C; see Figure 10; see Figure 11 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10; see Figure 11 Min Typ 6.7 12.1 5.3 1.2 Max 7.5 13.5 6 Unit m m m
RG
internal gate resistance f = 1 MHz; Tj = 25 C (AC) total gate charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; Tj = 25 C; see Figure 12; see Figure 13 ID = 0 A; VDS = 0 V; VGS = 4.5 V; Tj = 25 C
Dynamic characteristics QG(tot) ID = 25 A; VDS = 12 V; Tj = 25 C; see Figure 12; see Figure 13 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 14 VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 14 Coss Crss td(on) tr td(off) tf VSD trr Qr output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 15 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 14 VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG(ext) = 5.6 ; Tj = 25 C 16.3 12.5 4 2.5 1.5 5.6 2.4 1375 2120 640 250 15 38 32 25 0.86 34 21 1.2 nC nC nC nC nC nC V pF pF pF pF ns ns ns ns V ns nC
QGS QGS1 QGS2 QGD VGS(pl) Ciss
gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance
ID = 25 A; VDS = 12 V; VGS = 4.5 V; Tj = 25 C; see Figure 12; see Figure 13
Source-drain diode
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
5 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
4000 C (pF) 3000
03ar67
80 ID (A) 60
03ar63
Ciss
2000
Crss
40
1000
20 Tj = 175 C 25 C
0 0 2 4 6 8 VGS (V) 10
0 0 1 2 3 VGS (V) 4
Fig 5.
Input and reverse transfer capacitances as a function of gate-source voltage; typical values
80
03ar61
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
2.5
03aa33
ID (A) 60
VGS (V) =
10 6 5 4.5
4 3.5
VGS(th) (V) 2 max
3 40
1.5
typ
1 20 2.5 0.5 2 0 0 0.2 0.4 0.6 0.8 VDS (V) 1 0 -60 0
min
60
120
Tj (C)
180
Fig 7.
Output characteristics: drain current as a function of drain-source voltage; typical values
Fig 8.
Gate-source threshold voltage as a function of junction temperature
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
6 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
10-1 ID (A) 10-2
03aa36
15 VGS (V) = RDSon (m) 10
03ar62
3.5
10-3 min 10-4 5 10-5 typ max
4 4.5 5 6 10
10-6 0 1 2 VGS (V) 3
0 0 20 40 60 ID (A) 80
Fig 9.
Sub-threshold drain current as a function of gate-source voltage
2 a 1.5
03af18
Fig 10. Drain-source on-state resistance as a function of drain current; typical values
10 VGS (V) 8
03ar64
ID = 25 A Tj = 25 C
6 12 V
1
VDS = 19 V
4
0.5
2
0 -60
0
60
120
Tj (C)
180
0 0 10 20 30 QG (nC) 40
Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 12. Gate-source voltage as a function of gate charge; typical values
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
7 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
104
VDS ID VGS(pl) VGS(th) VGS QGS1 QGS2 QGD QG(tot)
003aaa508
03ar66
C (pF)
Ciss 103 Coss
QGS
Crss 102 10-1
Fig 13. Gate charge waveform definitions
1
10
VDS (V)
102
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
80 IS (A) 60
03ar65
40
175 C 20
Tj = 25 C
0 0.2
0.4
0.6
0.8
1
VSD (V)
1.2
Fig 15. Source current as a function of source-drain voltage; typical values
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
8 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428
y E b2 A A1 A E1
mounting base D1 HD
D2
2 L2 1 3
L L1
b1 e e1
b
w
M
A
c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2
OUTLINE VERSION SOT428
REFERENCES IEC JEDEC TO-252 JEITA SC-63
EUROPEAN PROJECTION
ISSUE DATE 06-02-14 06-03-16
Fig 16. Package outline SOT428 (DPAK)
PHD108NQ03LT_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
9 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20090605 Data sheet status Product data sheet Change notice Supersedes PHB_PHD_PHU108NQ03LT_3 Document ID PHD108NQ03LT_4 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type number PHD108NQ03LT separated from data sheet PHB_PHD_PHU108NQ03LT_3. Product data sheet Product data Product data 2004070095 PHP_PHB_PHD108NQ03LT-02 PHP_PHB_PHD108NQ03LT-01 -
PHB_PHD_PHU108NQ03LT_3 (9397 750 14707)
20050418
PHP_PHB_PHD108NQ03LT-02 20020911 (9397 750 10159) PHP_PHB_PHD108NQ03LT-01 20011218 (9397 750 09065)
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
10 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PHD108NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 5 June 2009
11 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 June 2009 Document identifier: PHD108NQ03LT_4

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